The present invention relates to methods of fabricating semiconductor devices, and more particularly, to methods of fabricating memory devices.
Flash memory devices, that is, non-volatile memory devices, may be classified into NAND flash memory devices that may be suitable for storing data blocks and NOR flash memory devices that may be suitable for storing code data.
In a NAND flash memory device, 8, 16, 32, or 64 cells, for example, may form a long string. Since bit lines may not require contact holes formed in the cells of the string, a high packing density may be realized.
FIG. 1A is a diagram of a cell array in a conventional NAND flash memory device and FIG. 1B is a cross-sectional view of a cell string included in the cell array of the conventional NAND flash memory device illustrated in FIG. 1A. Referring to FIGS. 1A and 1B, cells including gate lines and bit lines that cross each other at a substantially right angle are connected to each other in series to form the cell strings. A source selection line (SSL) and a ground selection line (GSL) are formed at both ends of a cell string. A gate line includes a control gate and a floating gate, and the control gate is connected to other control gates to form a word line. The bit lines proceed in parallel with the cell strings.
In a NAND flash memory device, there may be no contact hole between cells, and accordingly, distances between word lines are narrow and cell-to-cell interference may be likely to occur. In order to reduce the interference between the cells, a low k dielectric layer may be used between cell gate lines.
In addition, when an insulating layer is formed between the cell gate lines with a deposition method, a seam or a void may be generated in the insulating layer due to the narrow distance between the cell gate lines. The seam or void may result in a bridge between the cells when a metal silicide of a control gate is formed.